Session Chair:
Dr. Mark Martin, JHU/APL
Pictures from the Poster SessionPaper P4
"Radiation Hardness Improvement of the SiGe Bipolar Transistors by the Use of the Radiation & Thermal Processing (RTP- technology)"
S.V. Bytkin
Ukraine, Zaporozhye
Abstract: bytkin_a.pdf, bytkin_a.doc
Presentation: p4_bytkin_s.pdf, p4_bytkin_s.ppt
Paper: p4_bytkin_p.pdf, p4_bytkin_p.docPaper P6
"Apollo: A Unique Project, Time, and Period in US Culture"
R. Katz
NASA Goddard Space Flight Center
Presentation: apollo.htm
Note: This is for exhibition in Posters Section.Paper P7
"SDRAM Single-Event Error Modes—Characterization, Rate Calculation and Mitigation"
Ray Ladbury
Orbital Sciences Corporation
Abstract: ladbury_a.pdf, ladbury_a.doc
Presentation: p7_ladbury_s.pdf, p7_ladbury_s.ppt
Paper:Paper P8
"Single-Event Upsets in SRAM FPGAs"
Michael Caffrey1, Paul Graham1, Eric Johnson1, and Michael Wirthlin2
1 Los Alamos National Laboratory
2 BYU
Abstract: caffrey1_a.pdf
Presentation: p8_caffrey_s.pdf, p8_caffrey_s.ppt
Paper: p8_caffrey_p.pdfPaper P9
"Advanced Integrated Control and Data Systems for Constellation Satellites"
Dr. Michael Hahn, Günther Elsner
Astrium GmbH
Abstract: hahn_a.pdf, hahn_a.doc
Presentation: p9_hahn_s.pdf, p9_hahn_s.ppt
Paper: p9_hahn_p.pdf, p9_hahn_p.docPaper P13
"Update on the Radiation Testing of the Pentium III Microprocessor"
Jim Howard1, Ken LaBel2, Marty Carts3, Ron Stattel3, Charlie Rogers3, and Tim Irwin4
1 Jackson & Tull Chartered Engineers
2 NASA GSFC
3 Raytheon ITSS
4 QSS, Inc.
Abstract: howard2_a.pdf, howard2_a.doc
Presentation: p13_howard_s.pdf
Paper:Paper P14
"Verification of SHUR Macro Cell Library in a Fault Tolerant Digital Signal Processor Application"
D. Breuner, P. Coakley, S. Lutjens, and M. Rose
Jaycor
Abstract: breuner_a.pdf, breuner_a.doc
Presentation: p14_breuner_s.pdf, p14_breuner_s.ppt
Paper:Paper P15
"Implementation of Adaptive Digital Controllers on Programmable Logic Devices"
David A. Gwaltney, Kenneth D. King and Keary J. Smith
NASA Marshall Space Flight Center
Huntsville, AL
Abstract: gwaltney_a.htm
Presentation: p15_gwaltney_s.pdf, p15_gwaltney_s.ppt
Paper: p15_gwaltney_p.pdf, p15_gwaltney_p.docPaper P16
"A Reconfigurable 1.5 GB Stacked SDRAM Board"
Dr. Robert F. Hodson, Darren R. Boyd, and Mark L. Jones
NASA Langley Research Center
Abstract: hodson_a.pdf, hodson_a.doc
Presentation: p16_hodson_s.ppt
Paper: p16_hodson_p.pdf, p16_hodson_p.docPaper P17
"Application of Reconfigurable Computing Technology to Multi-KiloHertz Micro-Laser Altimeter (MMLA) Data Processing"
Wesley Powell, Philip Dabney, Edward Hicks, and Maxime Pinchinat
NASA Goddard Space Flight Center
Abstract: powell_a.htm, powell_a.pdf, powell_a.doc
Presentation: p17_powell_s.pdf, p17_powell_s.ppt
Paper: p17_powell_p.pdf, p17_powell_p.docPaper P18
"A Versatile State-Machine Controller for the SABER Instrument".
Mark D. Jensen and Jay C. Ballard
Space Dynamics Laboratory, Utah State University
Abstract: jensen_a.htm, jensen_a.pdf, jensen_a.doc
Presentation: p18_jensen_s.pdf, p18_jensen_s.ppt
Paper:Paper P19
"An FPGA Wire Database for Run-Time Routers"
Eric Keller and Scott McMillan
Xilinx Labs
Abstract: keller_a.pdf
Presentation: p19_keller_s.pdf, p19_keller_s.ppt
Paper: p19_keller_p.pdfPaper P20
"Update on the Qualification of PEMs (Plastic Encapsulated Microcircuits) in Space"
Joseph J Fabula
Xilinx Corporation
Abstract: fabula_a.html, fabula_a.pdf, fabula_a.doc
Presentation: p20_fabula_s.ppt
Paper:Paper P21
"SEE and TID Extension Testing of the Xilinx XQR18V04 4Mbit Radiation Hardened Configuration PROM"
Carl Camichael1, Joe Fabula1, Gary Swift2, Steve Guertin2, and Candice Yui2
1 Xilinx, Inc.
2 Jet Propulsion Laboratory
Abstract: carmichael_a.htm, carmichael_a.pdf, carmichael_a.doc
Presentation: p21_carmichael_s.pdf, p21_carmichael_s.ppt
Paper: p21_carmichael_p.doc, p21_carmichael_p.pdfPaper P22
"Construction Analysis of the XQVR300 FPGA and the XQR18V04 PROM"
Frederick Felt
Failure Analysis Laboratory
QSS/NASA Goddard Space Flight Center
Abstract: felt_a.html
Paper: p22_felt_s.pdf, p22_felt_s.docPaper P23
Henning Leidecker
"Reliability of Wire Bonds in Modern ASICs and FPGAs"
NASA Goddard Space Flight Center
Abstract: leidecker_a.html
Presentation:
Paper:Paper P25
"Coding a 40x40 Pipelined Multiplier"
Jim Lewis
SynthWorks Design Inc.
Abstract: lewis_a.htm, lewis_a.pdf, lewis_a.doc
Presentation: p25_lewis_s.pdf, p25_lewis_s.ppt
Paper: p25_lewis_p.pdf, p25_lewis_p.docPaper P26
"Easily Designed ASICs for Flip Chip Applications"
William Devanney, John MacPherson, and David Schmulian
Clear Logic, Inc.
Abstract: schmulian_a.htm, schmulian_d.pdfPaper P27
"Job Management System Extension to Support SLAAC-1V Reconfigurable Hardware"
Mohamed Taher1, Kris Gaj2, Tarek El-Ghazawi1, and Nikitas Alexandridis1
1 The George Washington University
2 George Mason University
mtaher@seas.gwu.edu
202 994 7309 (Phone)
Abstract: taher_a.pdf, taher_a.htm
Presentation: p27_taher_s.pdf, p27_taher_s.ppt
Paper: p27_taher_p.pdf, p27_taher_p.docPaper P28
"Where Hardware is Really Software"
Jim Tomayko
Carnegie Mellon University
"Jim Tomayko" <jet@cs.cmu.edu>
Abstract: tomayko_a.html, tomayko_a.pdf, tomayko_a.doc
Paper: p28_tomayko_p.pdf, p28_tomayko_p.docPaper P29
"Single-Event Upset Susceptibility Testing of the Xilinx Virtex II FPGA"
Gary Swift1, Candice Yui1, and Carl Carmichael2
1Jet Propulsion Laboratory / California Institute of Technology, Pasadena, CA
2Xilinx, Inc., San Jose, CA
Abstract: swift_a.htm, swift_a.pdf, swift_a.doc
Presentation: p29_yui_p.pdf, p29_yui_p.ppt
Paper: p29_yui_p.pdf, p29_yui_p.docPaper P30
3:45 - 4:10 pm
"Coding HDL for Reviewability"
Ben Cohen
VhdlCohen Publishing
Abstract: barto0_a.htm
Presentation: p30_cohen_s.pdf, p30_cohen_s_appendix.pdf, p30_cohen_s.ppt, p30_cohen_s_appendix.ppt
Paper:
Home - NASA Office of Logic Design
Last Revised:
April 30, 2003
Digital Engineering Institute
Web Grunt:
Richard Katz
