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Paper A2 Synopsis

Sample Integrated Fourier Transform (SIFT) With High-Performance ASIC Implementation

2001 MAPLD International Conference

Kossiakoff Conference Center
The Johns Hopkins University - Applied Physics Laboratory
11100 Johns Hopkins Road
Laurel, Maryland 20723-6099

September 11-13, 2001

Abstract

A zero-latency Fourier Transform algorithm and a high-performance ASIC implementation are presented. A 64-point complex Fourier Transform ASIC was simulated; results: 8mW, .49mm², 12.8µsec. A 1024-point Fourier Transform is proposed: 500mW, 32mm², 3.2µsec.

Table of Contents

1. Introduction
2. Overview
   1. DFT and FFT
   2. Butterfly and Architecture
3. SIFT Paradigm
4. Implementation And Results
5. Conclusions

List of Figures

Figure 1: FFT vs. SIFT data pipelines
Figure 2: Number of cycles vs. points for SIFT, single precision FFT(s), and double precision FFT(d)
Figure 3: SIFT: execution as samples arrive
Figure 4: Block diagram of the 64 point SIFT
Figure 5: Each coefficient accumulated in parallel
Figure 6: Origin offset does not alter waveform
Figure 7: Micro-graph of 64-point FT core
Figure 8: Architecture of 1024-complex-point FT
Figure 9 : Main portion of the Aspect Generator
Figure 10: FT of sin(x)
Figure 11: FFT Butterfly storage, none for SIFT
Figure 12: Inverse FT of Acos(2pf₁ x/N) + Bsin(2pf₂ x/N) at frequencies (16,63)
Figure13: Image of 64-point SIFT PCB
Figure 14: Inverse FT of Ecos(2pf₁ x/N) + Fsin(2pf₂ x/N) at frequencies (31,63)

List of Tables

Table 1. # MAC cycles vs. # Points in Transform

Summary

A new Fourier Transform process and architecture were presented which simplify hardware and support parallelism without latency. Reduced power, clock cycles and cycle times were shown. A method to further improve the computational efficiency was proposed.

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