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A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

"FPGAs for Fault Tolerant Circuits"

Session E. Reconfigurable Computing: Design Methods and Application-Specific Processors

Invited Talk

Kossiakoff Conference Center
The Johns Hopkins University- Applied Physics Laboratory
11100 Johns Hopkins Road
Laurel, Maryland 20723-6099

September 11-13, 2001

Dr. Steven Guccione

Xilinx Corporation

The vast majority of integrated circuits produced today rely on extremely high reliability in manufacturing for their successful operation. A device with tens of millions of transistors will typically be unusable if a single one of these transistors fails. If this failure is detected during production, the device is usually discarded, leading to the well-known "yield" of an integrated circuit manufacturing process. Similarly, if any portion of a circuit fails while in use, the entire system may become unstable or non-functional. For many applications, this mode of failure is acceptable, and repair or replacement of the component or system is a cost-effective solution. In many other applications, including those where repair or replacement of faulty components is expensive or impossible, some form of Fault Tolerance is necessary to keep systems operating in the presence of such failures.

In general, the techniques used to produce fault-tolerant circuits are based on having redundant components available to replace circuits detected as faulty. While providing such redundancy can be a costly and challenging design problem, Field Programmable Gate Arrays (FPGAs) provide a potential solution for implementing fault tolerant circuits and systems. The device architecture of FPGAs is itself a highly redundant circuit which includes a regular cellular array of reconfigurable logic and interconnect. The redundant nature of the underlying device architecture, combined with the ability to dynamically re-program the circuitry, should combine to make FPGAs devices a suitable platform for constructing fault tolerant circuits and systems.

While much research has been done in the area of fault tolerance using FPGAs, little or no support for this type of design has been made commercially available. This is in spite of the large potential gains in both system reliability and device process yield. While the underlying FPGA architecture does inherently provide support for fault tolerance, existing FPGA design software does little to take advantage of these properties.

The software must provide support for directly configuring, probing and reconfiguring large, popular, commercially available FPGA devices. This software has been the basis of some preliminary work in producing defect and fault tolerant FPGA circuits. These circuits have demonstrated the ability to configure and reconfigure FPGA devices in the presence of defects in both circuit logic and interconnect. This work involves three major components: the ability to construct working circuits in the presence of known defects, the ability to detect and isolate defects in an operating FPGA device, and finally the ability to reconfigure circuits at run-time to operate in the presence of newly detected defects.   The fundamentals of this software design problem will be explored.

Steven Guccione is a Staff Engineer at Xilinx. His interests are in high performance computing, in particular software tools for reconfigurable computing. Dr. Guccione received his B.S. degree in Electrical and Computer Engineering from Boston University, his M.S. degree in Electrical Engineering from the University of Minnesota and his Ph.D. degree in Electrical Engineering from the University of Texas at Austin. Dr. Guccione has previously held engineering positions at Texas Instruments, Honeywell, Advanced Micro Devices, IBM, MCC/Motorola and has consulted for several smaller companies.

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