PROGRAMMABLE TECHNOLOGIES WEB SITE

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.


MAPLD 2000 Technical Program

Session D. SoC, Synthesis, and IP

D_Tiggeler1.jpg (17321 bytes)
Session Chair
Hans Tiggeler
University of Surrey
Grunt Engineer, Apprentice
Session Pictures: Images_D.htm

D1: Software Support for the Integration of Reconfigurable Computing with Networks of Workstations
Miriam Leeser1, Elias Manolakos1, and Reid Porter2
1Dept of Electrical and Computer Engineering, Northeastern University
2Space and Remote Sensing Sciences Group, Los Alamos National Laboratory
Abstract:
Leeser_A.txt
Presentation: D1_Leeser_S.pdf
Presentation: D1_Leeser_S.ppt
Pictures: D1_Leeser1.jpg, D1_Leeser2.jpg

D2: Adaptive Management of Computing and Network Resources for Spacecraft Systems
Barbara Pfarr and Ryan Detter
Real-Time Software Engineering Branch
NASA Goddard Space Flight Center
Abstract:
Pfarr_A.pdf
Abstract: Pfarr_A.doc
Presentation: D2_Pfarr_S.pdf
Presentation: D2_Pfarr_S.ppt
Paper: D2_Pfarr_P.pdf
Paper: D2_Pfarr_P.doc
Pictures: D2_Pfarr1.jpg, D2_Pfarr2.jpg

D3A: Concurrent Error Detection Architectures for Symmetric Block Ciphers
R. Karri, Y. Kim, P. Mishra and K. Wu
Department of Electrical Engineering
Polytechnic University

Abstract: Karri_A.pdf
Abstract: Karri_A.doc
Presentation: D3A_Karri_S.pdf
Presentation: D3A_Karri_S.ppt
Paper: D3A_Karri_P.doc

D4A: Algorithm LEVEL RE-computing with Shifted Operands - A Register Transfer Level Concurrent Error Detection Technique
Kaijie Wu and Ramesh Karri
Department of Electrical Engineering
Polytechnic University

Abstract: Wu_A.pdf
Presentation: D4A_Wu_S.pdf
Presentation: D4A_Wu_S.ppt
Paper: Wu_P.pdf

D5: Designing and Testing a Radiation Hardened 8051-like Micro-controller
Fernanda Gusmao de Lima
Federal University of RGS
Abstract: Lima_A.pdf
Abstract: Lima_A.doc
Presentation: D5_Lima_S.pdf
Presentation: D5_Lima_S.ppt
Paper: D5_Lima_P.pdf
Paper: D5_Lima_P.doc

D6A: CDMA and Hopfield Neural Nets in FPGAs
R. Patterson and I. Jouny
Dept. of ECE, Lafayette College
Abstract: Jouny_A.pdf
Abstract: Jouny_A.doc
Presentation: D6A_Jouny_S.pdf
Presentation: D6A_Jouny_S.ppt
Paper: D6A_Jouny_P.pdf
Paper: D6A_Jouny_P.doc


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Last Revised: January 09, 2002
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