"High-Level Programming Issues for Reconfigurable Computing Systems"
Dr. Mark Jones, Configurable Computing Laboratory, Virginia Tech
Presentation: E0_Jones_S.PDF
Presentation: E0_Jones_S.ppt
A major obstacle for truly runtime reconfigurable computing systems has been the slow reconfiguration speeds of most programmable hardware devices (e.g., the Xilinx 4K series). The introduction of the Xilinx Virtex series, which has the capability of partial reconfiguration, and the Sanders CSRC chip, which features clock-cycle context-switching, has provided researchers with hardware that supports rapid reconfiguration. As with the introduction of many new hardware features, the software to exploit these capabilities is still in the research and development phase.
There is a consensus in the DARPA ACS research community that VHDL and the standard FPGA tool chain are not well suited for programming RTR systems. The typical tool chain lacks at least two features required for runtime reconfigurable (RTR) systems: (1) runtime control of hardware through a high-level language, and (2) fast (runtime) generation of new hardware configurations. This talk will highlight several DARPA ACS projects that are building software to allow developers to exploit RTR hardware.
Mark Jones is currently an associate professor in the Electrical and Computer Engineering Department at Virginia Tech. He received his PhD in Computer Science from Duke University in 1990. Upon graduation, he joined the technical staff in the Mathematics and Computer Science Division at Argonne National Laboratory. In 1993, he joined the faculty in the Computer Science Department at the University of Tennessee and left to join Virginia Tech in 1997. His research interests lie in the area of high-performance computation. His recent teaching interests are in the areas of computer architecture and computer programming.
Home
Last Revised: January 09, 2002
Digital Engineering Institute
Web Grunt: Richard Katz