A Reconfigurable Data Path Processor for Space Applications

                Gregory W. Donohoe
                  K. Joseph Hass
       Institute for Advanced Microelectronics

                   Pen-Shu Yeh
           Goddard Space Flight Center

This paper presents the Reconfigrable Data Path Processor,
a highly parallel, configurable processor being developed
for high-throughput data processing aboard spacecraft.

Current and planned spacecraft systems will require more complex 
on-board data processing. High data rate sensors, such as multi-
and hyper-spectral imagers and space-based radar, require high-
throughput processing on large quantities of streaming data.
Space-qualified data processors lag many generations behind those
available on Earth, however, and existing processors may not meet
the demands of new missions. Although several research programs are 
underway to develop space-qualified Power PC's and Digital Signal 
Processors (DSPs), current designs do no translate easily into 
radiation-tolerant processes.

Recent research in reconfigurable computing offers a new
approach to high-throughput processing, using reconfigurable
computer architectures that rewire themselves according
to the needs of the problem at hand. Most reconfigurable
computing systems are based on commercial programmable logic
devices such as Field Programmable Gate Arrays (FPGAs). Current
FPGAs are very powerful, with approximately one million equiv-
alent gates, and they allow designs concepts to be implemented
quickly. FPGAs are not optimal for most reconfigurable computing
applications, however: their very fine-grained configurability
exacts a heavy price in interconnects and configuration logic,
and on support software.  Complex FPGAs are not available in 
radiation-tolerant form.

The Institute for Advanced Microelectronics at the University
of New Mexico is teaming with the NASA Goddard Space Flight Center
to develop a new reconfigurable processor for space applications.
Called the Reconfigurable Data Path Processor (RDPP), it is 
targeted to a radiation-tolerant CMOS technology. The RDPP
occupies a middle ground between fine-grained, FPGA-based 
reconfigurable computers, and coarse-grained general-purpose
processors and DSPs. The RDPP will employ sixteen reconfigurable
processing elements with a flexible interconnect network
in a highly parallel architecture. Typical applications will
be on-board sensor readout correction and point tracking.

This paper presents the RDPP concept and design approach,
including architecture, computational model, and support
software, along with some preliminary results.