Normally a flip-flop is one of two states; either storing a logical '1' or a '0'. These states are stable as flip-flop elements employ positive feedback. In properly designed and functioning systems, all flip-flop parameters are met and the device operates normally. The key parameters are setup time, hold time, and pulse width (for clocks, presets, clears, jam loads, etc.). If these parameters are violated, as when an asynchronous input is fed into a flip-flop without meeting the setup and hold times, or when a runt pulse is input into the clock or asynchronous preset/clears, the flip-flop may go "metastable."
Device behavior in the metastable state may manifest itself as increased CLK -> Q delay, device output being a non-logic level, or an output switching and then returning to it's original state. Theoretically, the amount of time a device stays in the metastable state may be infinite; in practical circuits, there is sufficient noise to move the device output of the metastable state and into one of the two legal ones - however, this time may be large with respect to the available timing slack in the circuit resulting in a system failure. Factors that affect a flip-flop's metastable "performance" include the circuit design and the process the device is fabricated on. It turns out that by allowing sufficient settling time the MTBF for a well-designed system with asynchronous inputs can be made extremely low. This is possible since resolution time is not linear with increased circuit time and the MTBF is an exponential function of the available slack time. This can be seen in the following equation:
MTBF = e^(K2*t) / ( K1 x Fclock x Fdata)
where t is the slack time available for settling, K1 and K2 are constants that are characteristic of the flip-flop, and Fclock and Fdata are the frequency of the synchronizing clock and asynchronous data. By this equation, it is clear that an increase of 't' has an exponential effect on the MTBF. The two constants account for the two key characteristics of a flip-flops metastable behaviour: the size of the window (usually sub-nanosecond and the time to get out of a metastable state which is a function of the gain-bandwith product of the device).
Here are some calcuations we did using the Chip Express CX2001 technology,
based on their flip-flop parameters and example in the CX Technology Design Manual, as
look at how this technology performs. The CX2001 series uses a channelled module
architecture (gate array) with each module consisting of three 2:1 muxes and an AND gate
(a bit differently set up than Act 1 but not all that dissimilar). There are no
hardwired flip-flops in the architecture; these are available in all Actel families except
for Act 1, in Xilinx, Lucent, etc., devices. This sample calculation uses a 50 MHz
clock, a 10 MHz average incoming data rate, and the available extra settling time is the
independent parameter. Later, we'll be adding calculation done for other types of
flip-flops from other device manufacturers. This will allow a comparison of
metastable state resolution performance. Also, we'll be adding a program to
calculate MTBF's for all the flip-flops we have parameters for as well as a custom
setting.
extra delay
MTBF
MTBF
(nsec)
(sec)
(years)
1
448.2e-6
14.2e-12
2
180.8e-3
5.7e-9
3
72.9e+0
2.3e-6
4
29.4e+3
933.2e-6
5
11.8e+6
376.5e-3
6
4.7e+9
151.9e+0
7
1.9e+12
61.2e+3
8
779.6e+12
24.7e+6
9
314.5e+15
9.9e+9
10
126.8e+18
4.0e+12
11
51.1e+21
1.6e+15
12
20.6e+24
654.8e+15
13
8.3e+27
264.1e+18
14
3.3e+30
106.5e+21
DISCUSSION
With the 20 nSec period, let's say we allocate 10 nSec of additional delay for the first
synchronizing flip-flop to recover; this leaves 10 nSec for clk->q, routing delays,
tsu, and any unfavorable tskew. Since the flip-flops in a synchronizer will be physically
close, this is probably very conservative. As can be seen from the chart, 10 nSec of slack
will give a pretty reliable circuit.
| AN1504_D_ECLinPS.pdf | "Metastability and the ECLinPSE Family" Abstract This application note examines the concept of metastability and provides a theoretical discussion of how it occurs, including examples of the metastable condition. An equation characterizing metastability and a test circuit derived from that equation are presented. Metastability results are then applied to the ECLinPS family. |
| Actel_Metastability.pdf Actel_Metastability_Errata.pdf |
Actel Metastability Characterization Report. Families: A54SX32 (0.35 µm), RT54SX32 (0.6 µm), A1460A (0.8 µm), MX16 (0.45 µm), A1240XL (0.6 µm), and A1020A (1.0 µm). Added October 5, 2001. |
| xilinx_metastable_considerations.pdf | Xilinx Application Note XAPP077, January, 1997 for CPLD's. Summary: Metastability is unavoidable in asynchronous systems. However, using the formulas and test measurements supplied here, designers can calculate the probability of failure. Design techniques for minimizing metastability are also provided. Families: XC7300, XC9500. (.pdf 23 kbytes). |
| xilinx_metastable_recovery.pdf | Xilinx Application Note by P. Alfke and B. Philofsky. Description of metastable states, measurement techniques, tables of metastable parameters, and a summary graph. Families: XC4005E, XC4005, XC5206, XC3142A, XC3042. (.pdf 29 kbytes). |
| xilinx_metastable_recovery_2.pdf | "Metastability Recovery in Xilinx FPGAs," Xilinx Corp. (.pdf 143 kbytes). |
| meta_ti.pdf | "Metastable Response in 5-V Logic Circuits," This
document describes metastable response in digital circuits. After a definition of a
metastable state, a test circuit is provided, its responses analyzed, and test results
given. Examples show the influence of metastability on the response of asynchronous circuits and measures for improving reliability are assessed. Texas Instruments. (.pdf 243 kbytes). |
| cypress_meta.pdf | UltraLogic/PLDs Section Contents and Abstracts. Are Your PLDs
Metastable? This application note provides a detailed description of the metastable behavior. |
"Flip-Flops and Metastable States, " CX Technology Design Manual, Chip Express, 1997, pages 9-18 to 9-24.
"Metastable States," The Art of Electronics, Horowitz and Hill, 1989, page 552.
some of the other references that i have to go through and type in. send more if you have some!
http://soliton.physics.arizona.edu/~dls/1.html
Daniel L. Stein Noise-Assisted Escape from a
Metastable State. Robert Maier (Mathematics Department, University of Arizona) and I have
developed a program.
--http://soliton.physics.arizona.edu/~dls/1.html
An article from the EDA Today Summary Report Vol.
3, No. 2, February 1997. Figure 8. Click here to go back to the main article, "Xilinx
to Ride...
--http://www.edat.com/97pubs/2-97_XilinxHR4.htm
http://www.ti.com/sc/docs/psheets/abstract/apps/sdya006.htm
Digital and Impulse Circuits. Abbreviation: CIO. Credits: 6. Time: 3/2, 1st term, stage 2.
Prerequisites: Logical systems. Contents of Lectures: 1....
--http://www.fee.vutbr.cz/UIVT/courses/CIO/.iso-8859-1
http://www.csu.edu.au/ci/vol2/djjpaper/node2.html
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Previous:
Introduction. Sources of uncertainty. One of us (MJU) [1]...
--http://www.csu.edu.au/ci/vol2/djjpaper/node2.html
http://digibowser.ecn.purdue.edu/ee566/Report/section3.html
.0 Design Narrative. The description of the details of this design have been broken down
into
the three major sections of the design: the central...
--http://digibowser.ecn.purdue.edu/ee566/Report/section3.html
http://dlib.computer.org/dynaweb/tc/tc1995/@Generic__BookTextView/229808;td=3
IEEE Transactions on Computers 0018-9340/95$04.00 © 1995 IEEE Vol.
44, No. 6: June 1995, pp. 754-768 Manuscript received Sept. 15, 1993; revised June 5,...
--http://dlib.computer.org/dynaweb/tc/tc1995/@Generic__BookTextView/229808;td=3
http://www.nist.gov/srd/webguide/nist23/23guide.htm
Provides critically evaluated data for scientists and engineers
--http://www.nist.gov/srd/webguide/nist23/23guide.htm
Chris Java App/rchDataBase.html
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