NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

General Application Notes

 

Title, Authors, Reference, Link Abstract, Summary, Conclusions


Monitoring of a Digital Closed Loop Feedback Circuit

INTRODUCTION
   Some modern digital systems implement feedback circuits that enable circuits to perform with precision timing.  The key design consideration is to make the overall circuit insensitive to variables such as the variability associated with the manufacture of the components, temperature, voltage, radiation, and end of life changes in propagation delay.
   However, these positive characteristics of digital closed loop feedback systems may mask either damaged components or indications that components may not be healthy.  Monitoring key signals via engineering telemetry enables the test engineer to determine the amount of performance margin in the system, detect "out of family" circuit performance, and to "trend" the performance of the system.
   An example circuit from the Lunar Orbiter Laser Altimeter (LOLA) will be given showing the concept.  Additionally, the LOLA circuit scheme will be used to demonstrate how testability can readily be designed into circuits such as these.


Use of Spare Logic Resources

 INTRODUCTION Whether designing digital logic at the board level or when designing an application specific circuit that is implemented in a gate array, designers should leave "margin." These extra logic resources include gates, flip-flops, RAM blocks, input/output cells, and other resources as applicable to the circuit technology being used. These resources enable logic device designers to readily respond to changing requirements, fix design errors, enable freedom to trade off resources and power and speed, as well as easing the routing of the chip. At the end of the project, however, this margin or reserve serves no useful purpose and they are going to be in the embedded system. This application note will suggest two ways in which these resources can be effectively used.


ESD: A Tale of Two Lids

 

 Summary:

A socket manufacturer's lids were found to be ESD "unfriendly."  Alternate lids were ordered, from the same manufacturer, and were found to be ESD "friendly."


Cable Failure Attributable to Workmanship Error During Assembly of COTS Connector

NASA Advisory # NA-GSFC-2004-05
March 16, 2004
na-gsfc-2004-05.pdf

 Problem Description and Details:
A GSFC project had cable assembly failures due to shorted connectors. Trompeter Electronics, Inc. manufactured these COTS connectors per catalog p/n PL3155-47. A GSFC failure analysis determined that the connector failures were caused by a solder bump on the ring ferrule, which wore through the insulation sheath and shorted to the connector case. This solder bump protrusion is illustrated in Figures 1 and 2 on page 2. The root cause failure mechanism was attributable to poor GSFC workmanship during the connector assembly operation. Step 4B of the Trompeter Assembly Instruction TAI-125 requires the following: “Solder white conductor to inner shield, between ridges, being careful not to allow solder to extend above ridges”. As illustrated in Figure 3, the solder extended beyond the ridge line, thereby causing a solder protrusion into the insulation and a resultant shorting condition to case.


Handling of Parts - Subsequent Testing or Analysis

part handling testing

 Abstract:
When removing any part from a board that may be subjected to additional testing or analysis, it is very worthwhile to have the technician spend a bit of extra time removing the part with care, particularly with high pin-count leaded packages. As we can see from the photographs below, preparing this part for additional testing will be a challenge.


Tin Whiskers - A "New" Problem

February 25, 2004
tin_whiskers_ak.doc

 Introduction
     Electroplating an object's surface with a thin layer of corrosion resistant material (e.g., tin, zinc) is a standard method of protecting mechanical parts against corrosion. Platings (e.g., tin-lead solder, tin, gold, palladium) are also used on electrical parts to protect against corrosion and improve their solderability.
     It has been known for more than fifty years that a tin layer plated on a surface will spontaneously grow hair-like single-crystal filaments known as "tin whiskers". These whiskers are electrically conductive and physically strong.


TRST* and the IEEE JTAG 1149.1 Interface.

NA-GSFC-2004-04
na-gsfc-2004-04.pdf

 Problem Description and Details:
During project reviews, the NASA Office of Logic Design has found instances of flight hardware that had microprocessors and FPGAs with improper configuration of the TRST* pin and the IEEE JTAG 1149.1 Interface. Therefore, it is essential that the designers, analysts, and reviewers read the attached technical article, which emphasizes the design fundamentals of the proper termination of the TRST* pin and the IEEE JTAG 1149.1 Interface.

Timing Analysis of Asynchronous Signals

Introduction
Timing analysis of all signals must be performed.  A common mistake in the analysis of digital systems is the timing analysis of asynchronous signals.  With respect to flip-flops, these inputs are usually called PRESET and CLEAR.  For MSI devices, there are other signals that are similar such as the JAM input to counters or shift registers.  Although these signals are labeled "asynchronous" they do have restrictions on their use.  Failure to meet the specifications can result in incorrect operation.  Obviously, data being "jammed" into flip-flops must meet setup and hold times with respect to the asynchronous command pulse.

Analysis of POR Circuit Topologies

Abstract
The seemingly simple issue of FPGA and ASIC power-on reset circuits is nevertheless often a frequent cause of problems.  The discussion in this application note will cover both the key issues and a variety of circuits, analyzing their strong and weak points.  The discussion will in most cases be general logic design but will deal with some particular issues with Field Programmable Gate Arrays (FPGAs).

Asynchronous & Synchronous Reset Design Techniques - Part Deux

Clifford E. Cummings, Don Mills, and Steve Golson

reset_sync_async_v2.pdf

Abstract
This paper will investigate the pros and cons of synchronous and asynchronous resets. It will then look at usage of each type of reset followed by recommendations for proper usage of each type.

Some Characteristics of Crystal Clock Oscillators During the Turn-On Transient

Abstract
Here are some examples of oscillator response for the start up transient.   It seems that there are as many "signatures" during the transient as the number of oscillators that I can find to test.  Additionally, test conditions such as power ramp rate, time between power cycles, temperature, all play a role in the characteristics of the turn-on transient.


RC Timing Notes

Abstract
Generalized formula for the timing of RC circuits and some precalculated values for cases frequently encounters along with a caculator.

TTL Compatible" Inputs in CMOS Devices

ttl_compatibility.htm

Abstract:
All inputs in CMOS devices are not always truly TTL compatible.  To meet this criteria, VIL must be = 0.8V and VIH must be = 2.0V.  Data sheets and specifications must be read carefully to ensure that there will be proper noise margins.  Several examples are given below.


Up screening: A Manufacturer’s Viewpoint

Joe Fabula, Xilinx
cmse_upscreening.pdf
cmse_upscreening.ppt

 Notes On Upscreening Components.

Actel Corporation COTS and Up-Screening Policy

actel_upscreening_policy.pdf

Introduction
In 1994, Dr. William Perry, Secretary of Defense, announced a policy of adopting best commercial practices for procuring military electronics, including the purchase of Commercial Off The Shelf (COTS) products. The definition of COTS was vague. Some defense contractors thought it permitted the use of commercial products in military applications while others interpreted it as a directive to procure “Standard Products.” Actel defines “Commercial Off The Shelf” as any product that is manufactured through a standard production flow and is listed in the price book, data sheet, or product catalog. This would include space-level, MIL-STD-883, commercial, and industrial temperature products. COTS does not include source-controlled drawings or special screening.
Xilinx Upscreening Policy

Joseph J. Fabula
Director, Quality Assurance

Abstract
Xilinx has become aware that a number of after-market companies are offering our customers “up-screening” services for Xilinx products. These service providers attempt to elevate the grade level of an IC through the application of post-sale testing and/or screening. There are high risks associated with this practice for all but the simplest of components.


Kapton® Tape Identification

NASA Advisory NA-GSFC-2002-03
na-gsfc-2002-03.pdf


Problem Description and Details
Kapton® tape is widely used throughout the electronics industry and at Goddard. There are two generally available adhesive systems, acrylic and silicone. The silicone based thermoset adhesive has been found to cause contamination and contamination related failures due to outgassing and surface migration of the silicone adhesive. There have been four cases where Kapton® tape with a silicone based adhesive has been detected at the Goddard Space Flight Center.

Electrical Grounding Architecture for Unmanned Spacecraft

NASA-HDBK-4001
February 17, 1998

grounding_nasa_hdbk_4001.pdf
grounding_nasa_hdbk_4001.doc

FOREWORD

This handbook was developed to describe electrical grounding design architecture options for unmanned spacecraft. This handbook is written for spacecraft system engineers, power engineers, and electromagnetic compatibility (EMC) engineers. Spacecraft grounding architecture is a system-level decision which must be established at the earliest point in spacecraft design. All other grounding design must be coordinated with and be consistent with the system-level architecture.

This handbook assumes that there is no one single "correct" design for spacecraft grounding architecture. There have been many successful satellite and spacecraft programs from NASA, using a variety of grounding architectures with different levels of complexity. However, some design principles learned over the years apply to all types of spacecraft development. This handbook summarizes those principles to help guide spacecraft grounding architecture design for NASA and others.
Design, Analysis, and Test Guides A collection of guidelines, analysis, and documents to aid in the design, analysis, and test of spaceborne electronics and systems.


An Error Correction Code to Address Neutron Single Event Upsets in Semiconductor Memory

David W. Jensen, Ph.D.
Advanced Computing Systems
Rockwell Collins

Thirteenth Biennial Single Effects Symposium
Manhattan Beach, CA, April, 2002
jensen_rockwell_seesymp02.ppt


Introduction and Summary

  • Why concerned about Neutron Single Event Upsets (NSEUs)?
  • Error correction codes
  • Combining multiple mitigation techniques could enable an NSEU-tolerant, commercially-fabricated microprocessor

  • Presented efficient error correction block code to address Singe Event Upsets (SEUs) and Multiple Bit Upsets (MBUs) in semiconductor memory

Note: Could not make a .pdf file.  (May 3, 2002)

An Outline of Worst Case Analysis Requirements for Digital Electronics

WCA_Requirements.pdf

 Abstract
     Every designer’s goal is mission success: the production of a correctly functioning system.  One of the keys to achieving that goal is the worst case analysis (WCA). A detailed WCA, if performed during the design phase, can find design problems that may not be found during the test phase. Timing errors, interface margin problems, and other design flaws may manifest themselves only under limited operating conditions that are not present during test, such as temperature extremes, age, or radiation, or in limited operating modes that are not exercised in test. The only way to guarantee that no design flaws exist in a circuit is to carefully analyze the circuit and prove their absence.
     The purpose of a WCA is to prove the design will function as expected during its mission. The spirit of analysis is proof: all circuits are considered guilty of design flaws until proven innocent. The following is an outline of WCA requirements which introduces the circuit design items that must be reviewed as part of the WCA.

Digital Timing Analysis Tools and Techniques

Timing.pdf

 Abstract
     The timing analysis is a crucial part of a digital system’s worst case analysis. Every latched device has timing requirements -- set-up times, hold times, etc. - - that must be met in order to guarantee correct system operation, and the goal of the timing analysis is to determine whether they are met. Because each device input can have many sources whose timing can vary with circuit operation mode , the timing analysis can be very complicated and time consuming.  Thus many attempts at automating the timing analysis task have been made. But, the task is sufficiently complex that attempts to fully automate it have, so far, had only limited success. This report examines several timing analysis methods, and discusses their strengths and weaknesses.

Root-Sum-Square (RSS) Calculations of Digital Timing Delays

RSS.pdf

 Abstract
     The subject of RSS versus extreme value calculations arises often in worst case analyses because the calculation of a quantity, e.g., the delay of a digital parts chain, required to be less than some value, will yield a smaller result when calculated by the RSS method than by the extreme value method, making it easier to claim that requirements are met.
     The validity of RSS is often debated without exploring its mathematical basis. This report discusses the basis for RSS calculations and the method’s limitations. Although the discussion is centered around calculating the propagation delays of digital circuits, the basic theory and conclusions apply to any application of RSS.
NASA Lessons Learned The Lessons Learned Information System (LLIS) is a NASA-wide lessons learned repository. The LLIS offers search capabilities to permit various searches (e.g., NASA Center, date, Project, search string, etc.). Additional catagorization capability is under evaluation for future implementation by the LLIS Steering Committee.

The NASA Lessons Learned url link will take you directly to the LLIS Home Page.
GCRs: Integral LET Spectra.pdf Fluence vs. LET curves for a variety of orbits. (.pdf 27 kbytes)
socket_manufacturers.htm  
RadShielding1.htm  
MetastableStates.htm  
JTAG_SX_WhitePaper.PDF "Use of SX Series Devices and IEEE 1149.1 JTAG Circuitry."  This white paper reviews basic 1149.1 principles, radiation results on SX Series devices, and finishes with mitigation techniques and design considerations. (.pdf 629 kbytes)
StartupNote.pdf Consideration of component characteristics during the startup transient.

Home - NASA Office of Logic Design
Last Revised: August 10, 2007
Digital Engineering Institute
Web Grunt: Richard Katz
NACA Seal