NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Ronald Reagan Building and International Trade Center
with a session at the Smithsonian National Air and Space Museum

Washington, D.C.

September 26-28, 2006

Session Z: "Mixed Signal FPGAs and ASICs"

Session Chairs
Duane Armstrong, NASA Goddard Space Flight Center
Rajan Bedi, EADS Astrium

Session Z will be held on Wednesday, September 27, 2006 from 4:05 - 5:35 pm in Oceanic A.

This workshop is new for MAPLD 2006 and reflects not only how we design our space flight electronics but growing trends in the semiconductor industry.

The performance being demanded by future digital telecommunications payloads will not be achieved without major advances in mixed-signal space microelectronics. Significant progress is required to deliver qualified, wideband ADCs, DACs and SERDES to enable the next generation of broadband telecommunications satellite.

Increasing amounts of analog circuitry is now being included on die and flown. Low-power, high-performing BiCMOS technologies, the tolerance of the SiGe HJT to total-dose radiation, the use of integrated EDA tools and common design & verification flows, all offer the potential to advance mixed-signal space microelectronics. The benefits of integrating analog circuitry with digital logic include: higher performance, lower power consumption, less mass, reduced costs, improved reliability, greater levels of reusability, and enhanced system testing and quality – all of which contribute to the spirit of “Faster, Better, Cheaper”!

MAPLD 2006 is embracing this trend in space microelectronics and invites researchers working in the area of mixed-signal design for space applications to share their work with us.

We look forward to welcoming you to MAPLD 2006.

Program:

Submission 148
"Mixed-Signal Microelectronics for Space Applications: Future Challenges"
Rajan Bedi, Mark Walker and Lewis Farrugia
EADS Astrium
Abstract: 148_bedi_a.html

Submission 149
"Time-Interleaved ADC Architectures for Space Communications"
Rajan Bedi and Lewis Farrugia
EADS Astrium
Abstract: 149_bedi_a.html

Submission 164
"Actel Fusion Programmable System Chip 0.13 µm Devices"
Dan Elftmann and Antony Wilson
Actel Corporation
Abstract: 164_elftmann_a.html

Submission 238
"Fusion PSC Design Tools"
Venkatesh Narayanan and Jake Chuang
Actel Corporation
Abstract: 238_narayanan_a.html

Submission 1011
"Functional Recovery of Analog Circuits Using Self-Adaptive System Based on COTS Field Programmable Gate Array for Extreme Cold Temperatures"
A. Stoica, R. Zebulum, D. Keymeulen, R. Ramesham, S. Katkoori, J. Neff, S. Graves, F. Novak, and C. Antill
Jet Propulsion Laboratory
Abstract: 1011_stoica_a.html

 

   

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