NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Ronald Reagan Building and International Trade Center
with a session at the Smithsonian National Air and Space Museum

Washington, D.C.

September 26-28, 2006

Session M: "Low Power Design"

Session Chairs:
Matthew French, University of Southern California's Information Sciences Institute
Mike Wirthlin, Brigham Young University

Session M will be held on Wednesday, September 27, 2006 from 4:05 - 5:35 pm in Oceanic B.

PROGRAM

Submission 186
"FPGA Implementation and Power Modeling of FWT for Pattern Recognition"
S. Chandrasekaran and A. Amira
Brunel University
Abstract: 186_chandrasekaran_a.html

Submission 195
"Low Power Optimisation of DSP Core Networks on FPGA for High End Signal Processing Systems"
Stephen McKeown, Scott Fischaber, Roger Woods, John McAllister and Eoin Malins
Queen’s University Belfast
Abstract: 195_mckeown_a.html

Submission 257
"Algorithm Agile Low Power and High Data Rate Optimized System for RadHard Applications"
Meg Vootukuru
Syneren Technologies Corporation
Abstract: 257_vootukuru_a.html

Submission 1017
"Multi-Level Parallelism for Power and Energy Aware Design – Verified Using Novel Functional Level Power Analysis & Modelling (FLPAM)"
Shrutisagar Chandrasekaran and Abbes Amira
Brunel University, London
Abstract: 1017_chandrasekaran_a.html

 

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