NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

2006 MAPLD International Conference

Ronald Reagan Building and International Trade Center
with a session at the Smithsonian National Air and Space Museum

Washington, D.C.

September 26-28, 2006

Session H: Birds of a Feather: Reconfigurable Computing

Session Chairs:
Alan Hunsberger, National Security Agency
Douglas Fouts, Naval Postgraduate School

The 2006 MAPLD conference birds-of-a-feather (BOF) session on reconfigurable computing (RC) will be divided into 2 sections. BOF H1 will be held on Tuesday afternoon, September 26th, from 4:10 PM to 5:40 PM in the Amphitheater. BOF H2 will be held on Wednesday afternoon, September 27th, from 4:05 PM to 5:35 PM, also in the Amphitheater.  Both sessions will be co-chaired by Alan Hunsberger of the National Security Agency and Douglas Fouts of the Naval Postgraduate School.


This session will include presentations on the new National Science Foundation Center for High Performance Reconfigurable Computing, CHREC, that was recently established at the University of Florida and George Washington University.

  • Dr. Alexander Schwarzkopf, the NSF Lead Program Manager for the Industry/University Cooperative Research Centers program, will discuss the history and activities of the I/UCRC.

  • Dr. Alan George, the Director of CHREC, will give an overview of the planned research activities of CHREC.

Of course, there will be time for questions and discussions.

ALAN D. GEORGE is Professor of Electrical and Computer Engineering at the University of Florida, the flagship university in the fourth largest state in the US, where he serves as Director of the HCS Research Laboratory, Chair of the University Committee on High-Performance Computing, and Director of the new NSF Center for High-Performance Reconfigurable Computing (CHREC). He received the B.S. degree in Computer Science and the M.S. in Electrical and Computer Engineering from the University of Central Florida, and the Ph.D. in Computer Science from the Florida State University. Dr. George's research interests focus on high-performance architectures, networks, services, systems, and applications for reconfigurable, parallel, distributed, and fault-tolerant computing. He is a senior member of IEEE and SCS, a member of ACM and AIAA, and can be reached by e-mail at

The BOF-H1 session will also include an update on OpenFPGA from Jon Huppenthal, the President and CEO of SRC Computers.



Submission 122
"Generating Non-correlated Streams of Pseudo-Random Numbers in Reprogrammable Hardware"
Andrew Strelzoff, John Heath, and David Dobson
University of Southern Mississippi
Abstract: 122_johnston_a.html

Submission 124
"Checkpointing State Recovery for On-Board Computers"
Shazia Maqbool1, Chris Jackson2 and Craig Underwood1
1 Surrey Space Centre, University of Surrey
2 Surrey Satellite Technology Ltd.
Abstract: 124_maqbool_a.html

Submission 142
"Efficient FPGA Implementations of Floating-Point Reduction Operations"
Michael R. Bodnar1, James P. Durbano2, John R. Humphrey2, Petersen F. Curt2, and Dennis W. Prather1
University of Delaware
2EM Photonics, Inc.
Abstracts: 142_bodnar_a.html

Submission 221
"A High-Level Development Framework for Run-Time Reconfigurable Applications"
Stephen Craven and Peter Athanas
Virginia Polytechnic Institute and State University
Abstract: 221_craven_a.html

Submission 225
"A Fixed Point VHDL Component Library for a High Efficiency Reconfigurable Radio Design Methodology"
Scott D. Hoy and Marco A. Figueiredo
Scott D. Hoy1 and Marco A. Figueiredo2
1Honeywell - TSI
2MEI Technologies
Abstract: 225_hoy_a.html

Submission 232
"FPGA Acceleration of the LINPACK Benchmark Using Handel-C and the Celoxica Floating Point Library"
Kieron Turkington, Konstantinos Masselos, George A. Constantinides, and Philip Leong
Imperial College London
Abstract: 232_turkington_a.html


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