2006 MAPLD International Conference
Ronald Reagan Building and International Trade Center
with a session at the Smithsonian National Air and Space Museum
Washington, D.C.
September 26-28, 2006
Seminar: Design Verification Tutorial
The 2006 MAPLD International Conference seminars will be held on Monday, September 25, 2006 in Meridian C.
Seminar Leaders:
Tom Fitzpatrick, Verification Technologist, Mentor Graphics Corporation.
Abstract
The ever-increasing size and complexity of designs is simply a fact of life. The only way to make sure that today’s (and tomorrow’s) designs will function correctly is to build a verification environment that allows you to adopt advanced verification technologies to augment your engineers’ ability to exercise the myriad scenarios under which your design is expected to operate. The question is how to adopt these technologies, like assertions, functional coverage, automated results checking, constrained-random stimulus generation and formal verification, with a minimum of hassle and in a complementary way so they can all work together.
This full-day tutorial will introduce you to each of these technologies, and show you an effective methodology for building a modular, reusable testbench environment that will enable you to adopt them effectively. We will start by introducing each of these technologies in the context of a high-level discussion of verification methodology. We will then provide an in-depth introduction to the IEEE 1800 SystemVerilog language, which provides explicit support for each of these technologies.
We will then proceed to a discussion of testbench architecture, and show how you can use SystemVerilog to build a transaction-level verification environment that allows you to verify designs at multiple levels of abstraction. The use of transaction-level modeling (TLM) for verification allows the testbench to be constructed in a way more consistent with how you think about the problem, and allows all verification components to communicate through consistent interfaces, which provides reusability. These concepts will be demonstrated by a practical example showing the verification of an FPU design implemented both at the transaction-level and in RTL (in VHDL). We will show how to architect the testbench to allow the same stimulus generators and results checkers to be reused, as well as how to use the original TLM as a golden reference model against which the RTL design will be compared.
Presentation: verification_seminar_mapld06.pdf
Logistics
Location: Meridian C
Time: 9:00 am to 5:30 pm.
Seminar Schedule
- Start: 9:00 am
- Break: 10:30 am to 10:45 am
- Lunch: 12:30 pm to 1:30 pm
- Break: 3:30 pm to 3:45 pm
- End: 5:30 pm
Seminar Outline (Preliminary)
I. Introduction
a. The Difference between Design and Verification
b. Verification Technology Overview
i. The Verification Process
ii. Assertion-Based Verification (ABV)
iii. Testbench Automation (TBA)
1. Constrained-Random Stimulus
2. Functional Coverage
iv. Coverage-Driven Verification (CDV)
c. What is “Verification Methodology”
i. Applying technology in effective ways
ii. Answering questions about the design
II. SystemVerilog Overview
a. Standardization Process, Background and History
b. SystemVerilog Motivation
c. The 4 Quadrants of SystemVerilog
i. Design Constructs
ii. Verification Constructs
iii. Assertions
iv. Direct-Programming Interface (DPI)
III. SystemVerilog for Verification Basics
a. Assertions
i. What is an assertion?
ii. Sequences
iii. Properties
iv. Simulation and Formal Verification
b. Testbench Constructs
i. Randomization and Constraints
1. Language construct overview
2. Adopting Incrementally in Existing Environments
ii. Functional Coverage
1. Data-Oriented Coverage
2. Control-Oriented Coverage
iii. SystemVerilog Interfaces
iv. Object-Oriented Programming in SystemVerilog
1. Classes
2. Inheritance
3. Polymorphism
IV. Building a Reusable Verification Environment
a. What makes a good methodology?
b. Partitioning the Testbench
i. Control vs. Observe
ii. Verifying at Multiple Levels of Abstraction
c. Transaction-Level Modeling in SystemVerilog
i. TLM Interfaces
ii. Modeling Transactions
iii. Modularity and Reusability via TLM
d. Canonical Verification Components
i. Stimulus Generation
ii. Active Abstraction Conversion – Drivers
iii. Passive Abstraction Conversion – Monitors
iv. Analysis
1. Coverage Collectors
2. Scoreboards
V. Transaction-Level Verification in Action – Verifying an FPU
a. Assembling the testbench for a TLM
b. Reusing TLM testbench with RTL design
c. Reusing TLM as golden model in testbench
VI. Using SystemVerilog with VHDL Designs
a. Passing data between languages
b. Use-model Overview
i. SystemVerilog Assertions with VHDL
ii. SystemVerilog Testbench with VHDL design
VII. Conclusion
a. ROI analysis
b. Where to find more information
Seminars: 2006 MAPLD International Conference
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February 03, 2010
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