"Reconfigurable Handel-C FSL Accelerators for MicroBlaze"
Roman Bartosinski and Jiri Kadlec
Institute of Information Theory and Automation Academy of Sciences of the
Czech Republic (UTIA)
Abstract
MicroBlaze processor serves in many FPGA designs as the central 32 bit CPU with access to the global off chip memory and peripherals. MicroBlaze provides 8 FSL links for coprocessors. A challenge is to find straightforward design flow for these HW accelerators, which could be nearly as easy, as use of C or Fortran MEX functions utilized for acceleration of Matlab interpret on parallel platforms. We present design flow for partially dynamically reconfigurable on-chip accelerators in Handel-C. Each accelerator is connected to FSL link by set of dual ported BRAMs. Two of these BRAMS serve as swappable program memories for PicoBlaze microcontroller. This opens the possibility to reprogram on fly the SW part of each accelerator. MicoBlaze is using same communication channels for data transfer as well as for PicoBlaze program reload. Our currently implemented solution enables to run accelerators with no change of Handel-C source code on common starter kits with these parameters:
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Up to 8 accelerators for one MicroBlaze, 10-20 Mbytes/s data transfer rate from/to global MicroBlaze memory via one FSL link.
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Time to reprogram complete PicoBlaze program is 250-500 microsecond.
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Time to swap two PicoBlaze program contexts - 2 clock cycles
Board FPGA Family Part Provider System CLK
Digilent Spartan 3 xc3s200 Digilent/Xilinx 50 MHz
SPAR3E-SK Spartan 3E
xc3s500E Avnet 50 MHz
RC10 Spartan 3L xc3s1500L Celoxica
64 MHz
RC200E Virtex 2 xc2v1000 Celoxica
75 MHz
ML402 Virtex 4 xc4vsx35 Xilinx
100 MHz
