"An Upset-Mitigated FPGA-based High Performance Compute Platform for Space Applications"
Gary Swift and Greg Allen
JPL/Caltech
Abstract
The use of reconfigurable FPGAs with embedded processors in space systems is an enabling technology that will allow significant computing power and avionic performance in a small form factor and with low power requirements. A reference compute platform is presented in this paper based on a Xilinx Virtex-II Pro FPGA with two embedded PowerPC 405 processors. This platform is scalable, has high computing performance and is easily integrated into spaceflight avionics and instruments. Most of its features, including acceptable total dose and single-event latchup performance are given by the choice of FPGA. The largest effort in the platforms’s development is the development and in-beam verification of upset-mitigated IP cores build a robust system. This effort was necessary because of the innate “softness” of SRAM configuration cells to single-event upsets. Five primary IP cores were developed and tested to “complete” FPGA-based computer: (1) Lockstep dual processor operation, (2) a triplicated BlockRAM scrubbing engine, (3) a configuration manager, including self-scrubbing and single-event functional interrupt (SEFI) detection, (4) a memory interface for external SDRAM and (5) a memory interface for external non-volatile RAM, i.e., a flash memory controller. Block diagrams and in-beam test results will be shown; an overview is shown below.
