"On Using Simulink to Program SRC-6 Reconfigurable Computer"

David Meixner, Volodymyr Kindratenko, and David Pointer
National Center for Supercomputing Applications (NCSA), University of Illinois at Urbana-Champaign (UIUC)


In this presentation we will describe how to program SRC-6 reconfigurable computer using MathWorks Simulink® with Xilinx System Generator™ for DSP and Xilinx Blockset.  We will present example applications that take advantage of this programming model. 

By design, SRC-6 reconfigurable computer is programmed in MAP C programming language.  Code development on SRC-6 platform closely resembles code development on a conventional microprocessor-based system, with corrections made for data transfer between the system memory and FPGA-controlled memory.  SRC’s Carte development environment allows to bring in 3rd party subroutines, called macros, that can be used to extend the functionality of the original language.  These macros, typically implemented in Verilog Hardware Description Language, are brought into the MAP C program via a configuration file that defines the interface between the macros and MAP C language.

We developed a method of using the Verilog source for SRC macros generated from the Simulink-based designs.  We begin with developing Simulink model that implements the required algorithm.  We then use Xilinx System Generator to i) produce a Verilog file that describes the behavioral model of our design and ii) generate the netlists for the low-level functional blocks.  We then setup Carte’s configuration files to implement the required MAP C interface to the macro.  As a result, we are able to use Simulink-based designs on SRC-6 reconfigurable computer.

Ability to introduce Simulink-based designs into Carte programming environment opens up new possibilities in programming the SRC-6 system.  Thus, one can explore system-level designs that use FPGA resources, e.g., BRAM, directly.  One can also use IP cores, such as FFT and CORDIC algorithms, provided by Xilinx without the need to re-write them in MAP C.  Another advantage in using Simulink-based designs is the ability to define arbitrary sized data types, which is not directly available in the MAP C environment.  This can potentially lead to reduced FPGA resources utilization as one can avoid the need to use larger numerical types for problems that require a reduced numerical resolution.  For example, in Simulink, one could define data types as being 20-bits wide, whereas in MAP C one would need to use data types of 32-bits. 

Since Simulink performs all calculations with fixed point arithmetic, floating point numbers must be converted to fixed point representation in order to take advantage of variable resolution.  However, when converting between floating point and fixed point numerical representations, there can be a loss of numerical resolution.  The size and fractional precision of the fixed point numbers determine its precision, so a higher precision requires a larger size.  This is a tradeoff that must be taken into consideration by the programmer.


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