“Evolution of the Space Shuttle AP101”

Roscoe C. Ferguson, William T. Smithgall
United Space Alliance


In 1981, the first launch of the Space Transportation System (STS) or Space Shuttle was a marvel of technological advancement. Part of this advancement was the use of a commercial off the shelf processor that was at the heart of the data processing system. This processor was the International Business Machines (IBM) AP101.  

In 1966, IBM introduced the 4 Pi computer line to provide support for embedded systems. This line was designed to provide the same architecture and instruction set as the IBM 360 computer. Before it’s use on the Shuttle Program, the 4 Pi had shelf life in programs such as the B-52, F-15, and the F-8 digital fly by wire experimental aircraft. In fact, the AP101 was an upgraded and repackaged version of its AP-1 ancestor used in the F-15. The AP101 was also used on the B-1B program. 

The AP101 was selected from a choice between itself, the Autonetics D232, the Control Data Corporation Alpha, the Raytheon RAC-251, and the Honeywell HDC-701 despite estimates from NASA engineering that it would not be able to support the load required by the Shuttle. It was chosen because of its shelf life in other aircraft and the available pool of IBM 360 instruction set programmers and existing tool sets available on IBM 360 based computers. 

The version of the AP101 that flew on the STS-1 mission was a Complex Instruction Set Computer (CISC) with support for 16 and 32-bit instructions. There were a total of 154 micro-programmed instructions available for use. It provided support for both 16 and 32-bit Fixed point operations and Floating Point operations supporting word sizes of 32, 40, and 64 bit words. The AP101 supported various addressing modes including support for base-relative addressing. It was interfaced to core memory with a size of 104 K 32-bit words with a 400 ns memory access time. The AP101 could execute approximately 480,000 instructions per second. For input/output, the AP101 was interface to a custom Input/Output processor (IOP). This processor consisted of 24 processors to service each of the Shuttle buses and a Master Sequence Controller processor to manage the 24 individual processors. The AP101 and the IOP were housed in separated units, yet shared the same memory space. 

In 1984, NASA approved an avionics upgrade project to enhance the AP101. The primary goals were to retain the existing CPU instruction set, but provide faster performance, increase the memory capacity to 128 K extendable to 256 K, and to combine the AP101 CPU and IOP into a single unit with decreased power and weight. The goal was to support a first flight in 1986. The upgraded version of the AP101 did not fly until 1991 due to technical challenges including requirements changes, parts manufacturing problems, SRAM performance problems, and software compatibility problems. Other factors included resource diversion to support recovery from the Challenger accident and system integration. However, all objectives were successfully met with the most significant being a performance increase to 1 million instructions per second and an increase in Mean Time Between Failure (MTBF) from approximately 5000 hours to 90,000 hours. The later has resulted in significant improvements in vehicle processing flow, and launch and mission operations schedule integrity.


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