“A Single Chip 1553 Interface” Rod Barto NASA Office of Logic Design Abstract A previous MAPLD paper described the selection process for a 1553 IP core. This paper describes the design process and functionality of the resulting 1553 interface FPGA. 2006 MAPLD International Conference Home Page
“A Single Chip 1553 Interface”
Rod Barto NASA Office of Logic Design
Abstract
A previous MAPLD paper described the selection process for a 1553 IP core. This paper describes the design process and functionality of the resulting 1553 interface FPGA.
2006 MAPLD International Conference Home Page