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A recently reported anomaly in the RADPAL’s operations has been confirmed but not fully characterized at this time. The purpose of this memorandum is to convey what we know today. Further documentation on the problem will be made available as more information is collected. Engineers expect to complete an initial evaluation by September 19^th 1997. The initial evaluation will characterize the performance of units shipped year to date and hopefully identify a work-around, screen, and temperature and operating profile. Wafer lots in inventory will also be evaluated for this anomaly. At this time we believe the anomaly affects QML A, V, and RHR product only. At 25°C the part meets the data sheet over the specified power supply range of 5 volts +/- 10%. Only RADPAL’s programmed with registered outputs (i.e., sequential logic) will exhibit the anomaly.

From the evaluation performed to date we have observed the following. The anomaly is limited to the asynchronous reset of the RADPAL’s macro-cell circuit during power-up. Failure mode: the power-on reset circuit fails to release (i.e. logically negate) at power supply voltages (VDD) between 4.8V and 5.0V at -55°C. As temperature increases the voltage threshold decreases. Once VDD exceeds the voltage threshold, operation to the data sheet is achieved (i.e., 5 volts +/-10% over the full military temp range). Unprogrammed parts behave better than programmed parts either due to self-heating or ground bounce.

The profile of the decrease is close to linear but has a second or third order profile (i.e., slight curve). At -40°C, with the limited data taken to date, the threshold ranges from 4.7 to 4.9. The variance from device to device is 200mV. At 25°C data shows that all parts would meet the minus 10% specification. At 4.8V (-4%) and -40°C, 80% of the units shipped to date would pass. The data presented in this memo is from a small sample size and could improve or get worse.

For additional information please contact myself (719)594-8252 or Tim Meade (719)594-8048.

HERE IS THE TEXT FROM THE UTMC PRODUCT ADVISORY:

UTMC has identified the following anomaly n the power up behavior of the UT22VP10 RADPAL.

Background:

A recent customer application uncovered a power-on-reset (POR) anomaly associated with the UT22VP10 RADPAL. Under specific power up conditions the RADPAL would enter an internal test mode. As a result, the output buffers would enter a high impedance state. Additionally, the best way to get out of this state was by removing power from the chip, and performing another power-up sequence.

Anomaly:

The anomaly was observed for a power-up application where a residual voltage between 300 and 500 mV was supplied to the VDD pin(s) of the RADPAL for several milliseconds prior to the 5V power supply ramping to 5 volts. Consequently, the RADPAL was able to enter a test mode. As a result, the output buffers are placed in the high impedance state.

Through HSPICE simulation and laboratory tests, UTMC has found the reason for this anomaly. The results show that there exists a small window in which a residual voltage of a few hundred millivolts on the VDD pin(s) will cause the RADPAL to miss an internal POR signal within its security circuit. Consequently, the lack of a reset signal allows the security circuit to come up in an uncontrolled fashion. Because the security circuit is uncontrolled for this scenario, the RADPAL has the potential to enter a test mode on power-up.

Solution:

The UT22VP10 RADPAL appears to be susceptible to this POR anomaly under the following 2 conditions:

1. Existing residual voltages on the VDD pin(s) of the RADPAL prior to the application of the 5V power supply
2. Slow power-up sequences

In order to avoid powering up the UT22VP10 RADPAL in a test mode, the following specifications must be met:

1. The application of voltages on the VDD pin(s) of the RADPAL must start at 0V and reach 3V within 150 microseconds (20mV/usec).
2. The power-up voltage must be continuously increasing with respect to time, through 3V, and monotomic thereafter.
3. There can not be any voltage applied to VDD prior to the intended power-up sequence.

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