Kenneth A. LaBel
NASA/GSFC
(301)286-9936
and
Christina Seidleck
Hughes/STX
(301)286-1009
November 22, 1994
I. INTRODUCTION
The objective of this study was to determine the threshold linear
energy transfers (LETths) and cross-sections for single event upset
(SEU) and single event latchup (SEL) due to heavy ions. LETth is
defined as the maximum LET at which no errors are seen at a fluence
of 1.00E07 particles/cm2. SEU LETthis defined as the minimum LET
value to cause an effect at a fluence of 1E7 particles/cm2. SEL
LETth is defined as the maximum LET value at which no latchup occurs
at a fluence of 1E7 particles/cm2. The saturation cross section of
the device is the point at which the cross section curve becomes
asymptotic.
II. TEST SAMPLES
Relevant characteristics of the devices are summarized in the
following table:
Device Type Mfg. Date Code Ser. No Technology
Test Metal Chip
HR2340 Honeywell ??? 3-402, #19,22 CMOS
DC-DC Converters
AHE2815DF/CH-SLV Advanced Analog 9345 9338119
AHE2815D/HB Advanced Analog ??? ???
2690R-D15F MDI 9324 2016,0201
MFL2815D Interpoint 9443 0194,0202
MFL2815S Interpoint 9442 0060,0061
MFL2812S Interpoint 9442 0021,0047
MFL2805S Interpoint 9442 0188,0239
FIFOs
7204 IDT ??? 3CC9405BP Bulk CMOS
3DC9410BP
7203ERPDE IDT 9424 ??? ??? CMOS/epi
MOSFET Driver
MIC4427 MICREL ??? ??? Bipolar
EDAC Controller
49C460DGB IDT 1AC9424BP ???,??? CMOS/epi
Voltage Regulator
LP2951 Nat. Semi. ??? 0072,0079,0082
EEPROMs
HN58C1001 Hitachi ??? ???
28C256ERPDB SEEQ 9436 ???,???
D-A Converter
AD565A Analog Devices 9145 S678 CMOS
Sample devices were delidded in order to accommodate beam
penetration limits of the test facility.
III. TEST TECHNIQUES AND SETUP
A. Facility Usage
The test facility used was the Brookhaven National Laboratories
(BNL) Single Event Upset Test Facility (SEUTF) between November
9 and 12, 1994. This setup utilizes a dual Tandem Van De Graaff
accelerator suitable for providing ions and energies for SEU
testing. The test devices are mounted on a device-under-test
(DUT) board inside a vacuum chamber.
The SEUTF uses a computer-driven monitor and control program to
provide a user-friendly interface for running the experiments.
Hard copies of the test data and graphs are also made available.
B. Test Hardware, Software and Control
Test hardware, software, etc,... consisted of a DUT board placed
in the test chamber, six feet of twisted pair ribbon cable, and
two PC-based testers, the Omnilab and VXI systems. Both testers
provide test patterns to the test boards and are capable of
capturing output when errors occur. The VXI enhances the error
capture by using an intrinsic compare and a custom-built FIFO
buffer board thereby reducing processing time and eliminating the
need for additional hardware on the DUT boards. Both systems are
capable of controlling the entire test setup, digital counters,
power supplies, waveform generators as well as the BNL computer
via an IEEE 488 bus.
The test setup for the HR2340 will be described separately.
C. Device Test Procedure
The test procedure was similar for all devices tested. All tests
were either dynamic in nature, (with the exception of strictly
latchup testing) meaning that the devices were operating during
the test at a nominal rate as they might in a spacecraft
application, or in a static mode were the devices were merely
biased during irradiation. In dynamic testing, power was first
supplied to the device. A stimulus pattern was then loaded and
the device began to function normally while exposed to the ion
beam. Outputs from the device were constantly monitored by
either the Omnilab or VXI and all errors accumulated until either
fluence was reached or a latchup condition occurred. In the case
of the latter, power and beam to the device were terminated and
the test run ended prematurely. Otherwise, error counts were
logged to the hard drive. Static mode testing varied by pre-
loading the DUT with a known pattern, irradiating the device,
then reading back from the device looking for errors. Two to
three samples are typically used for testing to gain statistical
validity. All DUTs were tested under a (nominal) 25 degrees
celsius.
D. Ion Beam Usage
The following table summarizes the ions typically used for
testing.
ION ATOMIC NO. ENERGY IN MeV LET in MeV*cm2/mg at 0 deg.
C 12 97 1.46
F 19 136 3.45
Cl 35 195 11.8
Ni 58 262 26.6
I 127 305 59.6
Au 197 329 81.2
Additional effective LET values were attained by varying the
angle of incidence of the ion beam to the device. All LETs
discussed are in MeV*cm2/mg.
IV. RESULTS AND DISCUSSIONS
1. HR2340 Test Metal Chip
The HR2340 is a sea of transistors gate array based on the RICMOS
IV process. This device was tested in support of the MONGOOSE III
program, a commercially-compatible R3000-based processor. There
are many functions in this test chip of which , for SEE purposes,
we tested the following:
Test chip areas register type # of stages or bit
(soft latch design): JK 150
D 200
RS 150
Test chip areas (RH design): 32x23 asynch RAM, 1Kx1 synch RAM
Test conditions: Temperature: 25deg C
Vcc for SEU: 5V and 4.5V
Vcc for SEL: 5.5V
Test modes: Static - device pre-loaded, then irradiated, then
checked for errors post-beam
Dynamic - continuous R-W at a 1 MHz frequency
Test patterns: all 0's, all 1's, and mixed 0's and 1's
A custom test board was designed using a 8051 microcontroller
along with the DUTs and support logic on a PCB. This allowed a
low-noise test setup, providing reliable results. Figure 1
(34k) shows the test board after mounting to the BNL test fixture.
Test results for soft latch areas (all Xsections are given per
flip-flop, LET in MeV*cm2/mg):
(Mode, pattern, Vcc) LET Saturation Xsection, cm2 Fig #
Dynamic, Mixed, 4.5V ~14 2E-6 2
Dynamic, Mixed, 5V 16 2E-6 3
Dynamic, All 0's, 5V 16 1.2E-6 3
Dynamic, All 1's, 5V 16 1.2E-6 3
Static Mixed, 5V ~19 8.4E-7 4
As seen in figure 3, the soft latch areas are approximately
10-25% more sensitive using a mixed test pattern than an all
1's or 0's pattern.
For comparison, Honeywell's previous test data on the soft
latches using a static mode with unknown test pattern at 4.5V
plus a high temperature of 80deg C was as follows:
Static, Unknown, 4.5V 17-19 2E-6
The following SEU rate predictions for Geosynchronous orbit
for the Honeywell Soft Latch were performed using hand
integration and Cosmic Ray predictions provided by Code 900's
Radiation Physics Office. Utilizing this Cosmic Ray predication
allows a more realistic prediction as well as a finer
partitioning of test data for integration. No solar flares are
considered. A nominal 143 mills of Al shielding were included
in the Cosmic Ray spectrum and in all predictions below.
Dynamic mode, Mixed pattern, with Vcc at 5V, LETth = 16
Particle Fluence in part/cm2/day Upset rate per bit day
LET range Bit XSect, cm2 Solar Max Solar Min Solar Max Solar Min
16-26 5E-7 5.74e-3 2.68e-2 2.87e-9 1.34e-8
26-32 8E-7 7 .13e-4 3.22e-3 5.7e-10 2.58e-9
32-40 1.5E-6 1.22e-5 5.89e-5 1.83e-11 8.83e-11
> 40 2e-6 7.07e-7 3.54e-6 1.41e-12 7.08e-12
Upsets per bit-day for Solar Max: 3.46e-9
Upsets per bit-day for Solar Min: 1.16e-8
Assuming the Mongoose III has 4000 bits, the upset rates are as follows:
Upsets per dev-day for Solar Max: 1.38e-5 (1 per 198 years)
Upsets per dev-day for Solar Min: 4.64e-5 (1 per 59 years)
For EOS orbit, upset rate would be approximately 1 per 60 year
(4.2e-6 cm2/device)
Static mode, Mixed pattern, with Vcc at 5V, LETth = 19
Particle Fluence in part/cm2/day Upset rate per bit day
LET range Bit XSect, cm2 Solar Max Solar Min Solar Max Solar Min
19-26 2e-7 3.40e-3 1.55e-2 6.80e-10 3.10e-9
26-32 4e-7 7.13e-4 3.22e-3 2.85e-10 1.29e-9
32-40 5e-7 1.22e-5 5.89e-5 6.11e-12 2.94e-11
> 40 8.4e-7 7.07e-7 3.54e-6 5.92e-13 2.97e-12
Upsets per bit-day for Solar Max: 9.72e-10
Upsets per bit-day for Solar Min: 4.42e-9
Assuming the Mongoose III has 4000 bits, the upset rates are as follows:
Upsets per dev-day for Solar Max: 3.88e-6 (1 per 700 years)
Upsets per dev-day for Solar Min: 1.77e-5 (1 per 150 years)
Upsets per dev-day for EOS: 1.34e-5 (1 per 200 years)
Predictions for static mode are nearly the same as those
using previous Honeywell data. Dynamic mode results show
a higher SEU sensitivity than the static mode (factor of
three).
The LETth for the hard latches in the RAM cells is
approximately 60 MeV*cm2/mg with a maximum cross-section
per bit of 2.49e-7 cm2.
2. AHE2815
This device is a DC-DC power converter where the nominal
inputs were 28V, 350mA and the outputs were 15V, 375mA.
During irradiation, this device was operated in-step with
a reference device with monitoring for four possible types
of errors (SEUs). An error is defined as a difference
between the reference and DUT outputs. Testing was also
performed utilizing a 34V/272mA input.
A error counter was used when the device went into a
nonfunctional mode (nondestructive). Errors of this nature
appeared to be a "Switchoff error" with the device getting
switched "off" from an "on" position and required a power
reset to again function normally. During this condition,
DUT power consumption dropped from a nominal 350 mA to
between 110-141 mA depending on the DUT sample tested.
Additionally, the inhibit pin of the device cycled low as
well from its nominal 10.5V. Destructive conditions such
as Single Event Gate Rupture (SEGR) were also monitored.
This test did not look for transient output errors of the
device as previously performed during testing in July 1994.
Figure 5 (37k) shows the test setup prior to entry into the
BNL vacuum chamber.
Please note that due to the constrictions of the beam
diameter, the top and bottom portions of this IC device
were irradiated separately. The two samples of the
AHE2815D that were tested supposedly utilized differing
pulse width modulator (PWM) ICs (one with an epi substrate
and one without). No difference was seen during testing
between these samples. This PWM difference is being verified.
Figure 6 shows the switchoff cross section per device versus
the test LET. For the top of the device, switchoff and
destructive errors were seen, while neither of these
conditions were seen for the bottom portion. The SEU
threshold for switchoff errors was previously reported to be
between the LET values 20 and 26.6. A destructive condition
thought to be gate rupture was seen at an LET of 26.6 on a
single DUT sample utilizing the 34V input condition. Further
device analysis is planned to confirm this condition.
3. 2690R-D15F
This device is a DC-DC power converter where the nominal
inputs were 28V, 175mA and the outputs were 15V, 300mA.
During irradiation, this device was operated in-step with a
reference device with monitoring for four possible types of
errors (SEUs). An error is defined as a difference between
the reference and DUT outputs. Testing was also performed
utilizing a 34V/149mA input .
A error counter was used when the device performed what
appeared to be a spontaneous power reset. During this
condition, DUT output dropped from a nominal 15V down to
0V and back to 15V with a typical reset hysteresis curve
and a pulse width of approximately 10 msec. Destructive
conditions such as Single Event Gate Rupture (SEGR) were
also monitored. This test did not look for transient
output errors of the device.
Please note that due to the constrictions of the beam
diameter, the top and bottom portions of this IC device
were irradiated separately.
Figure 7 shows the "reset" cross section per device versus
the test LET. For the top of the device,only reset errors
were seen, while no SEEs were seen for the bottom portion.
The SEU threshold for reset errors was between the LET values
4 and 8. No destructive conditions were seen on any sample
at LETs up to a max tested of 72 even when utilizing the 34V
input condition.
4. MFL2815D
This device is a DC-DC power converter where the nominal
inputs were 28V,410mA and the dual outputs were 15V.
During irradiation, this device was operated in-step with
a reference device with monitoring for four possible types
of errors (SEUs). An error is defined as a difference
between the reference and DUT outputs. Testing was also
performed utilizing a 34V/360mA input .
A error counter was used when the device output dropped
from its nominal 15V to a steady state 14V. This condition
required a power reset to the DUT to return to normal
operations. Destructive conditions such as Single Event
Gate Rupture (SEGR) were also monitored. No transient
output errors of the device were seen.
Please note that due to the constrictions of the beam
diameter, the top and bottom portions of this IC device
were irradiated separately.
The voltage drop condition, which occurred on the bottom
half of the DUT, had an LETth between 45 and 59.7. No
cross section was measured statistically since it only
occurred sporadically during testing. No destructive
conditions were seen on any sample at LETs up to a max
tested of 72.
5. MFL2815S
This device is a DC-DC power converter where the nominal
inputs were 28V,240mA with a single output of 15V. During
irradiation, this device was operated in-step with a
reference device with monitoring for four possible types of
errors (SEUs). An error is defined as a difference between
the reference and DUT outputs. Testing was also performed
utilizing a 34V/230mA input .
No transient errors were seen on this device type Destructive
conditions such as Single Event Gate Rupture (SEGR) were
also monitored. No destructive conditions were seen on any
sample at LETs up to a max tested of 72.
Please note that due to the constrictions of the beam
diameter, the top and bottom portions of this IC device
were irradiated separately.
6. MFL2812S
This device is a DC-DC power converter where the nominal
inputs were 28V,180mA and the output was 12V. During
irradiation, this device was operated in-step with a reference
device with monitoring for four possible types of errors
(SEUs). An error is defined as a difference between the
reference and DUT outputs.
A error counter was used when the device output dropped from
its nominal 12V to below 11.4V . These spikes lasted < 20 nsec
before output voltage returned to normal range. Destructive
conditions such as Single Event Gate Rupture (SEGR) were
also monitored.
Please note that due to the constrictions of the beam
diameter, the top and bottom portions of this IC device
were irradiated separately.
The voltage spike, which occurred on the bottom half of the
DUT, had an LETth of ~50. Saturation cross section of this
condition was 5e-6 cm2 per device. No destructive conditions
were seen on any sample at LETs up to a max tested of 72.
7. MFL2805S
This device is a DC-DC power converter where the nominal
inputs were 28V,125mA with a single output of 5V. During
irradiation, this device was operated in-step with a
reference device with monitoring for four possible types
of errors (SEUs). An error is defined as a difference
between the reference and DUT outputs.
No transient errors were seen on this device type
Destructive conditions such as Single Event Gate Rupture
(SEGR) were also monitored. No destructive conditions were
seen on any sample at LETs up to a max tested of 72.
Please note that due to the constrictions of the beam diameter,
the top and bottom portions of this IC device were irradiated
separately.
8. 7204
This device is a 9x4096 bit FIFO. Testing was performed for
both SEU and SEL. SEU testing was performed in a dynamic mode
(DUT being W-R continuously) at a nominal 1 MHz frequency. Vcc
was nominally 5V/13mA with a latchup current set at 30 mA.
Testing was performed using an all 1's or an all 0's pattern.
No statistical difference was seen between the two test patterns.
An error was defined as anon-compare between output data values
and expected data values on a bit basis.
Figure 8 plots the SEE test results. The SEU LETth is between 8
and 11.6. Due to the onset of SEL condition, no saturation cross
section was determined. The SEL LETth is 16.
9. 7203ERP
This device is a 9x2048 bit FIFO. Testing was performed for both
SEU and SEL. SEU testing was performed in a dynamic mode (DUT
being W-R continuously) at a nominal 1 MHz frequency. Vcc was
nominally 5V/13mA with a latchup current set at 30 mA.
Testing was performed using an all 1's or an all 0's pattern. No
statistical difference was seen between the two test patterns.
An error was defined as anon-compare between output data values
and expected data values on a bit basis.
Figure 9 plots the SEE test results. The SEU LETth is between 8
and 11.6. Due to the onset of SEL condition, no saturation cross
section was determined. The SEL LETth is ~35. An additional
error condition was also observed: at LETs of 20 or greater large
bursts of output errors were observed. This is most likely due
to SEU hits to control areas of the DUT. Thus, this condition
has an LETth of 20.
10. 49C460
This device, from IDT, is an Error Detection and Correction
(EDAC) controller which will correct all single bit errors and
detect all double bit errors while performing memory checking
(or scrubbing). Vcc for this device was nominally 5V/4 mA with
a latchup current set to 10 mA.
The device was tested in normal operational mode (i.e., memory
scrub) at a frequency of 1 MHz. The test pattern used was a
checkerboard (alternating 1's and 0's) with one bit error
(either 1-to-0 or 0-to-1) inserted. The operation flowed as follows:
- data always has a single bit error
- DUT corrects error
- single bit error line is active, multiple bit error line is inactive
- syndrome is formed
Four typical error conditions were monitored during testing
plus a "special condition" and SEL. The standard error conditions
were: data errors, syndrome errors, single bit error detection
fail, and multiple bit errors in a word. The special condition
was discovered during testing. The symptoms of this condition were:
a drop in Icc to 1 mA with continuous errors on all standard error
lines. These errors continued even after the beam was stopped until
a power reset was issued to the device. This condition has been
theorized as being an SEU to the control region of the DUT,
causing it to switch modes of operation (potentially a diagnostic
mode).
Figure 10 illustrates the cross section per device for the total
errors (sum of four standard error conditions). The LETth is
between 20-25 based on curve fitting. Control errors were seen
sporadically starting with an LET of 26.6, but occurred
infrequently enough to hinder statistical data collection for
control error cross section. No sign of SEL was seen up to the
highest LET tested (80).
11. LP2951
The LP2951 from National Semiconductor is a micropower voltage
regulator with programmable output. Vcc for this device was
nominally 7V/50 mA with a SEL current set to 70 mA.
Output for testing was set to 5.0V. An error was defines as
being > 0.4V out of range (i.e., < 4.6V or > 5.4V).
Error were seen at all tested LETs (min. 26.6). However, a noise
problem in the test setup prohibited collection of statistical
data. Thus, a retest is expected of this device. No SEL was seen
on this device up to an LET of 90 (max tested).
12. HN58C1001
This device, from Hitachi, is a 1 Mbit (128Kx8) EEPROM, Nominal
Vcc for this device (standby mode) is 5V/4 mA . SEL current was
set to 50 mA.
SEL-only testing was performed on this DUT. No sign of latchup
was observed up to the maximum tested LET value of 90.
13. 28C256
This device, from SEEQ (repackaged by SEI), is a 256 kbit
(32Kx8) EEPROM, Nominal Vcc for this device (standby mode)
is 5V/7 mA . SEL current was set to 70 mA.
SEL-only testing was performed on this DUT. No sign of latchup
was observed up to the maximum tested LET value of 90.
14. AD565
The AD565A is a high-speed 12-bit monolithic D-to-A converter.
Nominal Vcc was +/-12V/+4/-17mA. SEL current was set at +5mA/-20mA.
The device was operated with an up-counter input with an analog
sawtooth output. An SEU was defined as a difference of 0.5V or
greater between DUT and a reference.
Under these test conditions, no SEUs or SEL were seen up to a
maximum tested LET of 80. Please note that it is expected that
transient errors of less than 0.5V may occur from heavy ions.
V. SUMMARY
The findings of these tests are interpreted in the following.
We typically divide SEE test results into the following four categories:
Category 1 - Recommended for usage in all spaceflight applications.
Category 2 - Recommended for usage in spaceflight applications, but
may require some SEE mitigation techniques.
Category 3 - Recommended for usage in some spaceflight applications, but
requires extensive SEE mitigation techniques or SEL
recovery mode..
Category 4 - Not recommended for usage in any spaceflight applications.
Category 1 devices for this test trip are:
SEL only: MIC4427, HN58C1001, 28C256
SEE: AD565A (if up to 0.5V errors are OK), 2815S, 2805S
Category 2 devices for this test trip are:
SEE: 2815D, 2812S (LETth are high enough to possibly use without
mitigation, however, telemetry points are recommended as a minimum)
HR2340 (if implemented in the MONGOOSE III: should have
H/W and S/W watchdogs if used in critical applications. May not
neet mitigation in non-critical applications.)
Category 3 devices for this test trip are:
7203ERP (moderate SEL characteristics, reasonable SEU)
49C460 (Monitoring required for mode switching condition)
Category 4 devices for this test trip (SEL only) are:
7204 FIFO (Low SEL threshold)
AHE2815. Both versions of his device showed four separate types
of SEE effects, all of which must be of concern to the system
designer. LETth of all these conditions give a finite chance of
occurance in most orbits, albeit, at fairly low rates.
MDI2690. This devices self-reset syndrome occured at low LETs. This
condition is difficult to design around on the system level.
The LP2951 requires more testing, but has some propensity for SEUs
and none for SEL.
VI. ACKNOWLEDGEMENTS
Special thanks to the test team, in particular, to the excellent test
sets and on-site support of Hak Kim of Jackson and Tull.
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