K.A. LaBEL
CODE 735.1
NASA/GSFC
Greenbelt, MD 20771
C.M. CRABTREE
Hughes/STX
Lanham, MD 20706
I. INTRODUCTION
The objective of this study was to determine the threshold linear energy transfers (LETths) and cross-sections for single event upset (SEU) and single event latchup (SEL) due to heavy ions. SEU LETth is defined as the minimum LET value to cause an effect at a fluence of 1E7 particles/cm2. SEL LETth is defined as the maximum LET value at which no latchup occurs at a fluence of 1E7 particles/cm2. The LM139 comparator, LM108 op-amp, SPT7822 12 bit, 30 MSPS ADC, CP2420 user programmable device, 88C20, 88C30 driver and receiver pair, the ODL200 fiber optic receiver and transmitter pair and the TSC4429 MOSFET driver were tested for the Far Ultraviolet Spectroscopic Explorer (FUSE) project. Additionally, the A1280A field programmable gate array was again tested in conjunction with Code 300.
II. TEST SAMPLES
Relevant characteristics of the devices are summarized in the following table:
Device Type Mfg. Date Code Technology A1280A Actel CMOS LM139 NSC Bipolar LM108 NSC Bipolar SPT7922 Sig. Proc. Tech. CMOS CP2420 Crosspoint CMOS 88C20, 88C30 NSC CMOS TSC4429 NSC Bipolar ODL200 ATT/CTS Bipolar (IC only)
Sample devices were delidded in order to accommodate beam penetration limits of the test facility.
III. TEST TECHNIQUES AND SETUP
A. Facility Usage
The test facility used was the Brookhaven National Laboratories (BNL) Single Event Upset Test Facility (SEUTF) between January 6 and 7, 1994. This setup utilizes a dual Tandem Van De Graaff accelerator suitable for providing ions and energies for SEU testing. The test devices are mounted on a device-under-test (DUT) board inside a vacuum chamber.
The SEUTF uses a computer-driven monitor and control program to provide a user-friendly interface for running the experiments. Additionally, support was provided by engineers working for Code 300. Hard copies of the test data and graphs were also made available.
B. Test Hardware, Software and Control
Test hardware, software, etc,... consisted of a DUT board placed in the test chamber, six feet of twisted pair ribbon cable, and two PC-based testers, the Omnilab and VXI systems. Both testers provide test patterns to the test boards and are capable of capturing output when errors occur. The VXI enhances the error capture by using an intrinsic compare and a custom-built FIFO buffer board thereby reducing processing time and eliminating the need for additional hardware on the DUT boards. Both systems are capable of controlling the entire test setup, digital counters, power supplies, waveform generators as well as the BNL computer via an IEEE 488 bus.
C. Device Test Procedure
The test procedure was similar for all devices tested. All tests were dynamic in nature, meaning that the devices were operating during the test as they would in a spacecraft application. First, a stimulus pattern was then loaded to the device. Power was then supplied and the device began to function normally while exposed to the ion beam. Inputs from the device were constantly monitored by either the Omnilab or VXI and all errors accumulated until either fluence was reached or a latchup condition occurred. In the case of the latter, power and beam to the device were terminated and the test run ended prematurely. Otherwise, error counts were logged to the hard drive. All DUTs were tested under a (nominal) 25 degrees celsius.
D. Ion Beam Usage
The following table summarizes the ions used for testing.
ION ATOMIC # ENERGY, MeV LET, MeV*cm2/mg at 0 deg. F 19 139.3 3.44 Cl 35 212 11.3 Ni 58 262.8 26.9 Au 197 340.4 82
Additional effective LET values were attained by varying the angle of incidence of the ion beam to the device. All LETs discussed are in MeV*cm2/mg.
IV. RESULTS AND DISCUSSIONS
1. A1280A
Several objectives were defined to be studied during this test. First, this device utilizes a technique of hardening known as triple modular redundancy (TMR) which basically means the output uses a voting scheme as opposed to conventional single line output. In theory this should greatly reduce the amount of real errors seen on the output line in comparison to single line output.
This device was to be tested in two modes: mode 0 examined the input buffer and serial shift register whereas mode 1 dealt with the output buffer and clock line. Each mode was to be tested for a pattern dependency. It was anticipated that the I/O buffers and clock line should show no such dependency while the serial shift register would be more SEU susceptible to a checker board pattern (rather than an all 1s or an all 0s pattern). Clock speed was varied for some test runs but the device showed no dependency.
Figures 1 and 2 show the SEU cross section per module versus the test LET value for all DUTs in mode 0. In this mode the LET threshold for zero upsets for all 0s/all 1s patterns was ~5 while the threshold for zero upsets for the checked pattern was ^LT; 5. This is explained by the fact that the serial shift register being monitored in mode 0 is more SEU prone with a checked pattern, i.e., during a state change. For mode 1 no SEUs were seen at LET < 10 regardless of the pattern. This is to be expected since mode 1 counts the SEUs on the output buffer and clock line both of which are expected to display no pattern dependency.
These results are very preliminary, further testing is scheduled for this device in February 1994.
2. LM139
Figures 3 and 4 show the SEU cross section per device versus the test LET value for all DUTs. The LET threshold for zero upsets is between 50 - 55. It is not certain if latchup was seen, all samples of this device showed a permanent current decrease at LETs of 82 and greater even after the power was cycled. Further testing of this device is scheduled.
3. LM108
Figures 5 and 6 show the SEU cross section per device versus the test LET value for all DUTs. The LET threshold for zero upsets is < 26. The dasta from all dUTs corresponds well. Again, it is not certain if latchup was seen, all samples showed a permanent increase in current after exposure to LET values of 82 and higher. This device will be tested further.
4. SPT7922
Figures 7 and 8 show the SEU cross section per device versus the test LET value for all DUTs. The LET threshold for zero upsets is < 3.4. The maximum saturation cross section per device is ~1.5E-03 cm2. The SEL LETth is > 120 at a cross section of < 1E-07 cm2.
5. CP2420
Figure 9 shows the SEU cross section per bit and latchup cross section per device versus the test LET value for all DUTs. The LET threshold for zero upsets is ~12.5. Both samples latched up at an LET of 26.6. Since no LET values between 15 and 26.6 could be attained, the latchup threshold is between those two values.
6. 88C20, 88C30
Figure 10 shows the SEU cross section per device versus the test LET value for all receivers. The LET threshold for zero upsets is ~11.3. The maximum saturation cross section per device is ~1.0E-05 cm2. For the transmitters, the SEU and SEL LETths were > 120 at cross sections < 1E-7 cm2.
7. TSC4429
All samples of this device indicated SEU and SEL LETths > 120 at cross sections < 1E-7 cm2.
8. ODL200
Figures 11 and 12 show the SEU cross section per device versus the test LET value for the receivers and transmitters. The LET threshold for zero upsets for the receivers was < 3.4 with a maximum saturation cross section of ~2.5E-04 cm2. The LET threshold for zero upsets for the transmitters was between 45 - 80.
V. SUMMARY
The findings of these tests are interpreted in the following.
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